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Sep 03, 2013, 03:36 AM
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Computational requirements

The STM32 can do a 1024 point FFT in 5ms. There's also the unknown matter of computing magnitude, normalizing, making it probably 10ms. At 10 sweeps per second, that gives only 10 FFTs per sweep.

That comes with a 8192 byte tag.

2048 bytes: analog capture window
2048 bytes: imaginary value window
2048 bytes: simultaneous capturing of next window
2048 bytes: normalization table

Then, the 1st 256 samples from each window are stacked on a polar projection. Only the 1st 1/4 of the window has had useful range. That comes with a 2560 byte tag for the current projection & 2560 bytes for the previous projection for 10 FFT's per sweep. 50 FFT's per sweep would take 12800 * 2 bytes.

Motion tracking in a polar projection would take some doing, but be the most efficient solution. An additional 5120 bytes of ROM might be required for a lookup table to convert the polar pixels to square pixels for motion tracking.

Then, some 1024 bytes of scratch memory might be required, bringing it to 60416 for the 50 FFTs per sweep or 19456 for the 10 FFTs per sweep.

To rotate the FFT's & motion track a square projection would take 256kbytes to retain the full resolution. It would involve a similar lookup table to only track filled pixels.

No matter how limited the microcontroller, the resolution & speed of the sampling can always be scaled down to fit. The difference is only in the resolution of the output, not whether it can be done. The memory requirement could fit in the Papilio, but it seems it could be just scaled down to fit in an STM32.

The 256 point FFT is 1ms with the unknown matters probably taking 1ms, giving 50 FFTs per sweep, but increasing the polar projection to only 6400 because of the reduced window size. The polar lookup table would grow to 6400. The resolution would be awful.

The computational requirement for simultaneously tracking motion would slow down the FFTs below these numbers. The memory requirement can be calculated by a formula:

WINDOW_SIZE * 8 + WINDOW_SIZE / 4 * SWEEP_COUNT * 4 + 1024 + 1024 + 2048

Another lookup table would be required for the magnitude calculation & another 2048 byte lookup table is for the VCO curve. The high end 1024 window size with 50 windows per sweep would be roughly 63488 bytes.

The FPGA would definitely get finer resolution, despite more constrained memory. But the brief experiment with VHDL showed it's very time consuming. The FPGA also needs ADC's & a DAC. It may be more efficient to use a microprocessor for the analog I/O.

The very best resolution would come from the FPGA scanning I & Q output from 2 receivers. Handling 2 radar modules would take 8 op-amp circuits multiplexed into 4 ADC's. It's also equivalent to oversampling a single I output 4x.

Redoing everything in C & VHDL would not be appealing either, leaving the size of the board as the mane factor. The minimum number of sweeps per revolution is required before anything else can be known, so you look for the easiest way to determine that.
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Sep 03, 2013, 04:17 AM
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Sep 03, 2013, 05:47 PM
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is that 1024 pts per line, or 1024x1024? not clear what you mean by a sweep.....but 1/0.01 = 100 . best to figure out what resolution you want, then divide by factors of 2 until you get there, since the standard FFT algorithm (cooley and tukey?) runs much faster working with powers of 2. doing cross-correlations in Fourier space (convolutions) will give you positions of "peaks" to much better than 0.1 resolution element and are very fast....

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