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Old Apr 06, 2004, 07:01 PM
WTH
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Re: When You Hear The Heavy Accent & The Poor Phone Connection...HANG UP!! ----- 0MCX2ECzHk

> > In article <BC982D8A.BDFF%behni@comcast.net>,
> > Brian Paul Ehni <behni@comcast.net> writes:
> >> RISC processors do not require the same clock speeds to perform the

same
> >> work as CISC processors; a point Apple has tried to make for many years

now.
> >
> > That's way/weigh/whey over simplified. You are still doing the same

work
> > but, you are doing it with a set of simpler instructions. Usually, the
> > memory references are decoupled from the arithmetic and logical

operations.
> > You end up loading and storing as independent operations and do a series
> > of register to register operations in between. ... ok, that's still over
> > simplified and just one aspect of the appeal of RISC.
> >
> > It puts a greater burden on the compilers to generate reasonable code.
> >
> > Paul

>
> There are other factors, too, like data block size, etc.


In any case, pipeline length has a much more direct impact upon the
potential clock speed than whether the instruction set is simple or complex,
as does the type of instruction set somewhat upon the pipeline (ergo the
confusion.)

WTH


Old Apr 06, 2004, 07:01 PM
Paul Newhouse
Guest
n/a Posts
Re: When You Hear The Heavy Accent & The Poor Phone Connection...HANG UP!! ----- 0MCX2ECzHk

In article <sLBcc.2596$ZJ6.1510@bignews5.bellsouth.net>,
"WTH" <spamsucks@Ih8it.com> writes:
>> > In article <BC982D8A.BDFF%behni@comcast.net>,
>> > Brian Paul Ehni <behni@comcast.net> writes:
>> >> RISC processors do not require the same clock speeds to perform the

> same
>> >> work as CISC processors; a point Apple has tried to make for many years

> now.
>> >
>> > That's way/weigh/whey over simplified. You are still doing the same

> work
>> > but, you are doing it with a set of simpler instructions. Usually, the
>> > memory references are decoupled from the arithmetic and logical

> operations.
>> > You end up loading and storing as independent operations and do a series
>> > of register to register operations in between. ... ok, that's still over
>> > simplified and just one aspect of the appeal of RISC.
>> >
>> > It puts a greater burden on the compilers to generate reasonable code.
>> >
>> > Paul

>>
>> There are other factors, too, like data block size, etc.

>
> In any case, pipeline length has a much more direct impact upon the
> potential clock speed than whether the instruction set is simple or complex,
> as does the type of instruction set somewhat upon the pipeline (ergo the
> confusion.)


The simpler instruction set allows the compiler/coder to optimize for the
pipeline more directly. You have to take the entire architecture into
account.

Paul
--
Working the Rockie Road of the G&PX
 


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