DFN Package thermal question...

[ejaf]

Most of the datasheets I've been looking at regarding IC packages seem to point out that DFN packages are much better at thermal dissipation than other packages (one I'm looking at is offered in a sot-23 package as well as a dfn).

Question is: is this because of the underlying internal design of a DFN package, or is it because of the big (relatively) bottom that can, in some instances, be soldered to an underlying pad for heat sinking purposes?

I want to go with the DFN package, but if it needs the heat sink attachment I mention above, that might steer me another way.

TIA...Eric

[jeffs555]

None of those small packages have enough surface area for heat dissipation, and most of the heat is transfered through the pins to the copper on the PCB. The DFN because of the large pad in the middle is better at transfering heat to the copper. It needs to be soldered.

I have seen some people design vias through the center pad on the PCB so they can hand solder it from the bottom, but don't know how well that works.

[ejaf]

Yeah...I saw an instructable on how to create the vias. I was hoping to skip that step, if the package itself is better at thermal dissipation than it's corresponding sot-23.

Guess I have to do that anyway. Thanks for the info.

Eric

[ejaf]

OK...one more question...

The datasheet specifies this as the Thermal Package Resistances of the DFN chip:
θJA=76°C/W on a 4-Layer JC51-7 Standard Board, Natural Convection

With the following note: "this represents the minimum copper condition on the PCB (Printed Circuit Board)"

I understand what the 76 degree centrigrade per watt means, and I think I understand the natural convection (no fan, just ambient air, I believe), but just what does the note mean about the "minimum copper condition on the PCB"? And there is no mention in the notes about "heat sinking" the bottom of the chip to the circuit board.

Any translation appreciated.

Eric

[jeffs555]

There is no mention of "heat sinking" because using standard surface mount techniques the bottom of the chip would be reflow soldered to the pad on the PCB. I believe the part about "minimum copper condition" and JC51-7 standard board refers to a JEDEC standard test board. I think the document number is JESD51-7 which specifies a board standard for thermal testing of surface mount parts. The standard board is 76x114 mm(about 3x4.5 inches) with embeded power and ground planes. A lot of the heat transfer would be from radiation and conduction into the power/ground planes. On a smaller 2-layer board, the junction to ambient differential would probably be a lot higher.

[ejaf]

OK...thanks for the info!

Eric

[Pete P]

I drill a small hole under the centralized pad, and solder+plug it with the biggest copper wire I can fit in it. I dremel the solder and wire flush (really only care about the wire) on the component side, and then solder it in. I make a look pf the copper wire on the other side, and solder it in... Works well at dissipating heat.

[ejaf]

Thanks for the tip, but exactly what does this mean:
I make a look pf the copper wire on the other side

I was going to do the same thing, I think, where I leave a bit of solder under the centralized pad, along with the wire I used for the "plug" a little longer on the opposite side (after dremelling it down to almost nothing, so no pads are up in the air). Then after pinning a couple of legs to the pads, reheat the wire sticking out, thereby reflowing the solder onto the central pad.

Is that what you mean?

FYI...the central pad's dimensions I am dealing with are 1.3x1.5mm. Not much room for a home made via, huh? :rolleyes:
T...Eric