Freq Synthesizers/PLLs

[charles0198]

Does anyone have any experience with PLLs for frequency synthesized receivers... I need some help.

[lazy-b]

charles0198, I guess, you just post the problem directly here, I'm sure Lots of expert here can help you that.

Ellion

[Mr DIY]

I have designed a few for Rx and Tx applications. Use them for my multichannel altimeter system that provides real time hight measurement for my thermal planes. The Rx is the easy one to do. A Tx that requires modulation is a little more tricky.

Brian

[charles0198]

I am using Fujitsu MB1504 PLL with MC3362 to make a freq synthesized R/C receiver at 72MHz. I have calculated the loop filter R and C values using the following specs.

Frequency range: 61.310 to 62.290 MHz
Channel spacing: 20 kHz
Maximum frequency change during a step (fstep): 800 kHz
The desired time for the carrier to step to a new frequency (ts): 10msec
The frequency of the carrier, within the desired time ts, after a step (fa): 1 kHz
Damping factor: 0.707
VCO sensitivity (calculated, not measured) (Kvco): 1.126 MHz/V
Charge Pump Current (Icp): 3mA

With these specifications and using the formulae given in fujitsu loop filter calculation document the value of R and C comes out to be:

C24 = 114nF (value used: 100nF)
R18 = 1.2k
C26 = 1.14uF (value used: 1uF tantalum)
C27 = 114nF (value used: 100nF)
R20 = 1.2k

Loop Bandwidth = 517 Hz

The output of PLL (input to VCO) is smooth and the receiver has tuned by adjusting L3 but the tuning is highly unstable. There are two problems: First with moving the transmitter away from the receiver the output becomes distorted and it seems that VCO is not tuning. The PPM output is fine by placing the transmitter next to the receiver. Secondly changing the channels by rotary dip switch, the output doesn't change with same transmitter channel (72.190MHz). It is desired that with RX channel change there should be no output until the TX is also changed to the same channel. I have checked the PIC16F84 output (data, clock, LE and LD) and its working perfectly fine by changing dip switch position, since it is in the plugable module form.

Could it be possible that VCO sensitivity is not properly adjusted or changing the values of C14 (68pF) can improve the tuning? L3 inductance is 150nH. Any suggestions...

I am also considering to replace the PLL with MC145170.

[Mr DIY]

Just some points and questions Charles.

Firstly, your loop bandwidth is unnecessarily low. Design for a higher ... say 1 KHz to 5 KHz range.

Don’t have your Tx anywhere close to your test setup. The output power of the Tx will climb onto everything. Keep it at least a few meters away.

I note that your PLL is using the 10.245 Mhz as a reference. How are you dividing this. You state that your channel spacing is 20Khz. Is this the synth frequency step or your required RX specification? If you take the 10.245 and divide it by 20Khz, you will have a value containing a fractional part, hence 20KHz will not be your channel step. Can you provide more detail here? PLL chips normally require a proper reference frequency in order to achieve desired frequency steps. I am not convinced of your 10.245MHz frequency, but then I do not know the MB1504 device. What is your reference division?

Brian

[foofighter]

Difficult to see but it looks like you have LD connected to an output from the PIC?
LD is Lock Detect and is an output from the PLL phase detector. When the PLL is locked LD will go high.

VCO tuning should be such that you adjust the coil core until LD goes high. Set the tuning position midway from where LD goes low either side of the lock-in point. Recheck that the PLL is locked reliably on switch on.

Dont worry about the wn (OMEGAn) value, it looks OK. Fast switching is not an issue here!

[Andy W]

.. on a related note, anyone ever see schematics for a cell-phone jammer?
..a

[Mr DIY]

Difficult to see but it looks like you have LD connected to an output from the PIC?

Not a problem ... that port pin would be defined as an input.

VCO tuning should be such that you adjust the coil core until LD goes high. Set the tuning position midway from where LD goes low either side of the lock-in point.

Nooo ..no. You setup by programming the synth to the middle frequency of intended range. Then adjust a coil (or cap) while monitoring the PLL low pass filter output with a multimeter. You want about half the VCC supply (PLL supply) at the filter output.

Ooh ... your loop filter design is wrong. You are using a 3rd order filter if I recall correctly. The output should be between R18 and C26.

. on a related note, anyone ever see schematics for a cell-phone jammer?

Now why would you want one of these? :)

And no I have not seen any circuits, but a swept oscillator withing the frequency band used (with enough power) ought to do the trick.

Brian
Brian

[foofighter]

Nooo ..no.

:o

OK then.

Have a look at FC is it high or low when open circuit? You need it tied low for the correct sense VCO tracking.

Also have another look at the data sheet for correct LPF configuration. You have a pole and no zero with that circuit (simple first order). Also the decoupling of the 3362 varicap should be right at that pin otherwise there will be stability issues.

GL

ps the charge pump output is tristate (especially when locked or close to locked) if you want to measure Vvco use a 'scope on x10.

[tve]

The output should be between R18 and C26.

Brian


Hi Charles,

I think MyDIY is right on this.

[charles0198]

The loop bandwith is fine because the lock up time ts (10msec) is no critical for this application and by calculations it automatically reduces the BW to 500 Hz (inverse relation of BW and ts).

Yes 10.245 MHz is the reference frequency with 20 KHz channel spacing. MB1504 is a fractional-N PLL with a swallow counter so it can compensate that. I have simulated the PIC output and have observed on an oscilloscope and its perfectly fine as desired.

LD (lock detect) is an output of MB1504 going to the input of the PIC; when LD is high PIC stops upgrading the PLL registers and waits for any further frequency switch. Regarding this unstability problem LD is High means that it is locked.

I will check the PLL output (VCO input) with a multimeter. The loop design is consistent with the recommended loop filter calculations of the Fujitsu document and its a 3rd order filter with fouth pole created by VCO. Please see the http://www.fme.fujitsu.com/products/pll/app3.html

For a positive slop VCO (voltage ~ freq) the Fc should be left open or connected to ground according to the MB1504 datasheet. Yes MC3362 coupling could be a problem.

[Mr DIY]

Charles

MB1504 is a fractional-N PLL

Nice device. I have not played with any fractional chips, but yes, the 10.245 should be fine then.

The loop design is consistent with the recommended loop filter calculations of the Fujitsu document and its a 3rd order filter with fouth pole created by VCO. Please see the http://www.fme.fujitsu.com/products/pll/app3.html

Oops yes .. .you are right. The way you draw your schematic for the loop filter is slightly different to the norm and gave me the impression that it was wrong. You should draw R18 and C26 to the inside of filter diagram and show R20,C27 on the ouside. Much more clearer to see it that way .. as you certainly caught me out with it. :)

Brian

[foofighter]

Regarding this unstability problem LD is High means that it is locked.


Different matter then.
If the PLL is locked at the correct frequency then instability will come from several possible areas:
- Inadequate phase margin
- Physical circuit layout
- Inadequate RF decoupling of individual ICs

Still have a doubt for the loop filter. The Fujitsu app note is for the MB15C/F "super" PLL, the MB1504 app note showed a different circuit? Also maybe be worth checking if the calculated Kvco is close to the real value?

[tve]

oops...

[charles0198]

foofighter

I think you are right regarding the physical circuit layout and inadequate RF decoupling of individual ICs. Thats why I am replacing the PLL with MC145170 and redesign the circuit and PCB. There are much more references available for this PLL. Would you please explain about inadequate phase margin, how this can affect?

About the fujitsu app note, it is a general loop filter design for all their PLL families... just my assumption, may be wrong. Any suggestion to optimize the new design!

[foofighter]

For the physical circuit layout you need to minimise track lengths between the phase detector and the VCO (including the loop filter). This is because you will have the Tx very close the Rx at times and you want as much immunity as possible. Double sided PCB can be useful here as you can keep one side as a ground plane.
Decoupling the VCO varicap as close as possible to the IC, use the capacitor of the last loop filter zero for this. But if the cap has a large value (> 47n) it can be useful to double this with a smaller value cap in parallel (470p - 1n) to get a broader band decoupling.
Same goes for decoupling Vcc at ICs. Close to the pin as possible and use parallel pairs of 100n and 1n. Component type and size is important but I guess this is all SMT so this probably is not a factor.

As far as stability evaluation of this type of PLL with 1st order Poles and Zeros, you need to calculate the open-loop response of gain and phase.
The open loop gain curve should intercept the unity gain axis with a slope of between -6 to -10 dB/octave. (12dB or greater will be unstable).
The phase margin should be approx 45 deg. (Phase margin is the difference between open loop transfer function and 180 deg at unity gain). The loop will contain stray capacitances, parasitic effects etc and these will add phase errors. If the phase errors due to strays, parasitic effects etc are enough the control loop is no longer inverting and goes unstable.

The loop filter should contain a Zero at some freq and a Pole approx a decade higher in freq. This relationship 'usually' results in a phase margin of approx 45 deg. Any further Zeros added to the loop filter must be significantly far away in the freq domaine to avoid increasing the open loop gain to 12dB/decade at unity gain etc.
Everything does interreact so a PLL simulation software is invaluable. I have the one Unruh here (just have to find a non-windows workstation to run it...)

[najfi]

HI,
How do you calculate these value. can you please write the equations. because at fujitsue website equations are incomplete

[foofighter]

There should be enough data in the application notes to calculate starting values for each of the 1st order loop filter components.

"1st order" in the proper sense, ie passive transfer functions are:

Poles = 1 / (S/Wp + 1)
Zeros = S / Wz + 1